In software development, make is a utility that automatically builds executable programs and libraries from source code by reading files called makefiles which specify how to derive the target program. The purpose of the make utility is to determine automatically which pieces of a large program need to be recompiled, and issue the commands to recompile them.
To prepare to use make, you must write a file called the makefile that describes the relationships among files in your program, and the states the commands for updating each file. In a program, typically the executable file is updated from object files, which are in turn made by compiling source files. The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. For each of those files, it issues the commands recorded in the data base. make executes commands in the makefile to update one or more target names, where name is typically a program. If no -f option is present, make will look for the makefiles GNUmakefile, makefile, and Makefile, in that order. make updates a target if it depends on prerequisite files that have been modified since the target was last modified, or if the target does not exist.
A makefile consists of dependency lines of text which define a target (a rule) followed by a colon and optionally a set of files on which the target depends. The dependency line is arranged so that the target (left hand of : character) depends on components (right hand of : character).
The commands that follow are usually arranged so that they generate the target. An example: if "file.html" is newer, it is converted to text. The contents of makefile:
lynx -dump file.html > file.txt
The above is run by invoking make with the target name file.txt:
This is an example descriptor file to build an executable file called prog1. It requires the source files file1.cc, file2.cc, and file3.cc. An include file, mydefs.h, is required by files file1.cc and file2.cc. If you wanted to compile this file from the command line using C++ the command would be
% CC -o prog1 file1.cc file2.cc file3.cc
This command line is rather long to be entered many times as a program is developed and is prone to typing errors. A descriptor file could run the same command better by using the simple command
% make prog1
or if prog1 is the first target defined in the descriptor file
Let's go through the example to see what make does by executing with the command make prog1 and assuming the program has never been compiled.
- make finds the target prog1 and sees that it depends on the object files file1.o file2.o file3.o
- make next looks to see if any of the three object files are listed as targets. They are so make looks at each target to see what it depends on. make sees that file1.o depends on the files file1.cc and mydefs.h.
- Now make looks to see if either of these files are listed as targets and since they aren't it executes the commands given in file1.o's rule and compiles file1.cc to get the object file.
- make looks at the targets file2.o and file3.o and compiles these object files in a similar fashion.
- make now has all the object files required to make prog1 and does so by executing the commands in its rule.
Make is invoked from a command line with the following format
make [-f makefile] [-bBdeiknpqrsSt] [macro name=value] [names]
However from this vast array of possible options only the -f makefile and the names options are used frequently. The table below shows the results of executing make with these options.
Frequently used make options
use the default descriptor file, build the first target in the file
use the default descriptor file, build the target myprog
make -f mymakefile
use the file mymakefile as the descriptor file, build the first target in the file
make -f mymakefile myprog
use the file mymakefile as the descriptor file, build the tar get myprog
These are the essential details of make utility in UNIX.